EDN

Hierarchical physical design—issues and methodologies

In IC physical design, there is a tendency to focus on the synthesis and layout tasks, and to not give much consideration to the chip finishing tasks, at least not until the more pressing matters of ...
EDN

Hierarchical design methodology supports complex FPGAs

FPGA devices have grown to ASIC size and complexity, but traditional EDA tools and methodologies have failed to keep pace. Engineers designing high-end FPGAs are beginning to face the types of ...
Semiconductor Engineering

Efficient Hierarchical Verification For Low Power Designs

Growing design sizes, low power (LP) complexity and the need for early stage verification is making designers adopt hierarchical verification flows. Traditionally for hierarchical verification, ...
Electronic Design

Maximizing Hierarchical Design Throughput for Today’s Large Designs

Fig 1. As an example of today’s ASIC design complexity, IBM’s Cu-32 ASIC product offering delivers 2.9K raw gates per square millimeter. Such advanced process nodes enable SoC design teams to ...